diff -X dontdiff-2.6 -Nurp linux-2.6.13-rc2/arch/arm/mach-s3c2410/dma.c linux-2.6.13-rc2-lucasvr/arch/arm/mach-s3c2410/dma.c --- linux-2.6.13-rc2/arch/arm/mach-s3c2410/dma.c 2005-07-08 11:05:19.000000000 -0300 +++ linux-2.6.13-rc2-lucasvr/arch/arm/mach-s3c2410/dma.c 2005-07-08 11:05:50.000000000 -0300 @@ -12,6 +12,7 @@ * published by the Free Software Foundation. * * Changelog: + * 23-Mar-2005 LCVR Added support for S3C2400 * 27-Feb-2005 BJD Added kmem cache for dma descriptors * 18-Nov-2004 BJD Removed error for loading onto stopped channel * 10-Nov-2004 BJD Ensure all external symbols exported for modules @@ -105,11 +106,11 @@ struct s3c2410_dma_regstate { static void dmadbg_capture(s3c2410_dma_chan_t *chan, struct s3c2410_dma_regstate *regs) { - regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC); - regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC); - regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT); - regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON); - regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); + regs->dcsrc = dma_rdreg(chan, S3C24XX_DMA(DCSRC)); + regs->disrc = dma_rdreg(chan, S3C24XX_DMA(DISRC)); + regs->dstat = dma_rdreg(chan, S3C24XX_DMA(DSTAT)); + regs->dcon = dma_rdreg(chan, S3C24XX_DMA(DCON)); + regs->dmsktrig = dma_rdreg(chan, S3C24XX_DMA(DMASKTRIG)); } static void @@ -189,7 +190,7 @@ s3c2410_dma_waitforload(s3c2410_dma_chan chan->stats->loads++; while (--timeout > 0) { - if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) { + if ((dma_rdreg(chan, S3C24XX_DMA(DSTAT)) << (32-20)) != 0) { took = chan->load_timeout - timeout; s3c2410_dma_stats_timeout(chan->stats, took); @@ -260,7 +261,7 @@ s3c2410_dma_loadbuffer(s3c2410_dma_chan_ writel(buf->data, chan->addr_reg); - dma_wrreg(chan, S3C2410_DMA_DCON, + dma_wrreg(chan, S3C24XX_DMA(DCON), chan->dcon | reload | (buf->size/chan->xfer_unit)); chan->next = buf->next; @@ -366,19 +367,19 @@ static int s3c2410_dma_start(s3c2410_dma /* start the channel going */ - tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); + tmp = dma_rdreg(chan, S3C24XX_DMA(DMASKTRIG)); tmp &= ~S3C2410_DMASKTRIG_STOP; tmp |= S3C2410_DMASKTRIG_ON; - dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); + dma_wrreg(chan, S3C24XX_DMA(DMASKTRIG), tmp); pr_debug("wrote %08lx to DMASKTRIG\n", tmp); #if 0 /* the dma buffer loads should take care of clearing the AUTO * reloading feature */ - tmp = dma_rdreg(chan, S3C2410_DMA_DCON); + tmp = dma_rdreg(chan, S3C24XX_DMA(DCON)); tmp &= ~S3C2410_DCON_NORELOAD; - dma_wrreg(chan, S3C2410_DMA_DCON, tmp); + dma_wrreg(chan, S3C24XX_DMA(DCON), tmp); #endif s3c2410_dma_call_op(chan, S3C2410_DMAOP_START); @@ -552,7 +553,7 @@ s3c2410_dma_lastxfer(s3c2410_dma_chan_t } /* hopefully this'll shut the damned thing up after the transfer... */ - dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD); + dma_wrreg(chan, S3C24XX_DMA(DCON), chan->dcon | S3C2410_DCON_NORELOAD); } @@ -809,15 +810,15 @@ static int s3c2410_dma_dostop(s3c2410_dm s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP); - tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); + tmp = dma_rdreg(chan, S3C24XX_DMA(DMASKTRIG)); tmp |= S3C2410_DMASKTRIG_STOP; - dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); + dma_wrreg(chan, S3C24XX_DMA(DMASKTRIG), tmp); #if 0 /* should also clear interrupts, according to WinCE BSP */ - tmp = dma_rdreg(chan, S3C2410_DMA_DCON); + tmp = dma_rdreg(chan, S3C24XX_DMA(DCON)); tmp |= S3C2410_DCON_NORELOAD; - dma_wrreg(chan, S3C2410_DMA_DCON, tmp); + dma_wrreg(chan, S3C24XX_DMA(DCON), tmp); #endif chan->state = S3C2410_DMA_IDLE; @@ -948,7 +949,7 @@ int s3c2410_dma_config(dmach_t channel, } dcon |= S3C2410_DCON_HWTRIG; - dcon |= S3C2410_DCON_INTREQ; + dcon |= S3C24XX_DCON(INTREQ); pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon); @@ -1044,22 +1045,32 @@ int s3c2410_dma_devconfig(int channel, /* source is hardware */ pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n", __FUNCTION__, devaddr, hwcfg); + +#ifdef CONFIG_CPU_S3C2400 + dma_wrreg(chan, S3C2400_DMA_DISRC, ((hwcfg & 3)<<29) | devaddr); + dma_wrreg(chan, S3C2400_DMA_DIDST, ((0<<1) | (0<<0))<<29); +#else dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3); dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr); dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0)); - - chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST); +#endif + chan->addr_reg = dma_regaddr(chan, S3C24XX_DMA(DIDST)); return 0; case S3C2410_DMASRC_MEM: /* source is memory */ pr_debug( "%s: mem source, devaddr=%08lx, hwcfg=%d\n", __FUNCTION__, devaddr, hwcfg); + +#ifdef CONFIG_CPU_S3C2400 + dma_wrreg(chan, S3C2400_DMA_DISRC, ((0<<1) | (0<<0))<<29); + dma_wrreg(chan, S3C2400_DMA_DIDST, ((hwcfg & 3)<<29) | devaddr); +#else dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0)); dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr); dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3); - - chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC); +#endif + chan->addr_reg = dma_regaddr(chan, S3C24XX_DMA(DISRC)); return 0; } @@ -1081,10 +1092,10 @@ int s3c2410_dma_getposition(dmach_t chan check_channel(channel); if (src != NULL) - *src = dma_rdreg(chan, S3C2410_DMA_DCSRC); + *src = dma_rdreg(chan, S3C24XX_DMA(DCSRC)); if (dst != NULL) - *dst = dma_rdreg(chan, S3C2410_DMA_DCDST); + *dst = dma_rdreg(chan, S3C24XX_DMA(DCDST)); return 0; } @@ -1102,7 +1113,7 @@ static int s3c2410_dma_suspend(struct sy printk(KERN_DEBUG "suspending dma channel %d\n", cp->number); - if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) { + if (dma_rdreg(cp, S3C24XX_DMA(DMASKTRIG)) & S3C2410_DMASKTRIG_ON) { /* the dma channel is still working, which is probably * a bad thing to do over suspend/resume. We stop the * channel and assume that the client is either going to @@ -1182,7 +1193,7 @@ static int __init s3c2410_init_dma(void) /* dma channel irqs are in order.. */ cp->number = channel; cp->irq = channel + IRQ_DMA0; - cp->regs = dma_base + (channel*0x40); + cp->regs = dma_base + (channel*DMA_CHANNEL_OFFSET); /* point current stats somewhere */ cp->stats = &cp->stats_store; diff -X dontdiff-2.6 -Nurp linux-2.6.13-rc2/include/asm-arm/arch-s3c2410/dma.h linux-2.6.13-rc2-lucasvr/include/asm-arm/arch-s3c2410/dma.h --- linux-2.6.13-rc2/include/asm-arm/arch-s3c2410/dma.h 2005-07-08 10:55:05.000000000 -0300 +++ linux-2.6.13-rc2-lucasvr/include/asm-arm/arch-s3c2410/dma.h 2005-07-08 11:05:50.000000000 -0300 @@ -13,6 +13,7 @@ * ??-May-2003 BJD Created file * ??-Jun-2003 BJD Added more dma functionality to go with arch * 10-Nov-2004 BJD Added sys_device support + * 22-Mar-2005 LCVR Added support for S3C2400 */ #ifndef __ASM_ARCH_DMA_H @@ -296,6 +297,19 @@ extern int s3c2410_dma_getposition(dmach extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn); extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn); + +/* defines a single interface for both S3C2410 and S3C2400 cpus */ + +#ifdef CONFIG_CPU_S3C2400 +#define S3C24XX_DMA(x) S3C2400_DMA_##x +#define S3C24XX_DCON(x) S3C2400_DCON_##x +#define DMA_CHANNEL_OFFSET 0x20 +#else +#define S3C24XX_DMA(x) S3C2410_DMA_##x +#define S3C24XX_DCON(x) S3C2410_DCON_##x +#define DMA_CHANNEL_OFFSET 0x40 +#endif + /* DMA Register definitions */ #define S3C2410_DMA_DISRC (0x00) @@ -308,9 +322,20 @@ extern int s3c2410_dma_set_buffdone_fn(d #define S3C2410_DMA_DCDST (0x1C) #define S3C2410_DMA_DMASKTRIG (0x20) +#define S3C2400_DMA_DISRC (0x00) +#define S3C2400_DMA_DIDST (0x04) +#define S3C2400_DMA_DCON (0x08) +#define S3C2400_DMA_DSTAT (0x0c) +#define S3C2400_DMA_DCSRC (0x10) +#define S3C2400_DMA_DCDST (0x14) +#define S3C2400_DMA_DMASKTRIG (0x18) + #define S3C2410_DISRCC_INC (1<<0) #define S3C2410_DISRCC_APB (1<<1) +#define S3C2400_DISRC_INC (1<<29) +#define S3C2400_DISRC_APB (1<<30) + #define S3C2410_DMASKTRIG_STOP (1<<2) #define S3C2410_DMASKTRIG_ON (1<<1) #define S3C2410_DMASKTRIG_SWTRIG (1<<0) @@ -320,32 +345,59 @@ extern int s3c2410_dma_set_buffdone_fn(d #define S3C2410_DCON_SYNC_PCLK (0<<30) #define S3C2410_DCON_SYNC_HCLK (1<<30) +#define S3C2400_DCON_DEMAND (0<<30) +#define S3C2400_DCON_HANDSHAKE (1<<30) +#define S3C2400_DCON_SYNC_PCLK (0<<29) +#define S3C2400_DCON_SYNC_HCLK (1<<29) + #define S3C2410_DCON_INTREQ (1<<29) +#define S3C2400_DCON_INTREQ (1<<28) + #define S3C2410_DCON_CH0_XDREQ0 (0<<24) #define S3C2410_DCON_CH0_UART0 (1<<24) #define S3C2410_DCON_CH0_SDI (2<<24) #define S3C2410_DCON_CH0_TIMER (3<<24) #define S3C2410_DCON_CH0_USBEP1 (4<<24) +#define S3C2400_DCON_CH0_XDREQ0 (0<<24) +#define S3C2400_DCON_CH0_UART0 (1<<24) +#define S3C2400_DCON_CH0_MMC (2<<24) +#define S3C2400_DCON_CH0_TIMER (3<<24) + #define S3C2410_DCON_CH1_XDREQ1 (0<<24) #define S3C2410_DCON_CH1_UART1 (1<<24) #define S3C2410_DCON_CH1_I2SSDI (2<<24) #define S3C2410_DCON_CH1_SPI (3<<24) #define S3C2410_DCON_CH1_USBEP2 (4<<24) +#define S3C2400_DCON_CH1_XDREQ1 (0<<24) +#define S3C2400_DCON_CH1_UART1 (1<<24) +#define S3C2400_DCON_CH1_I2SSDI (2<<24) +#define S3C2400_DCON_CH1_SPI (3<<24) + #define S3C2410_DCON_CH2_I2SSDO (0<<24) #define S3C2410_DCON_CH2_I2SSDI (1<<24) #define S3C2410_DCON_CH2_SDI (2<<24) #define S3C2410_DCON_CH2_TIMER (3<<24) #define S3C2410_DCON_CH2_USBEP3 (4<<24) +#define S3C2400_DCON_CH2_I2SSDO (0<<24) +#define S3C2400_DCON_CH2_I2SSDI (1<<24) +#define S3C2400_DCON_CH2_MMC (2<<24) +#define S3C2400_DCON_CH2_TIMER (3<<24) + #define S3C2410_DCON_CH3_UART2 (0<<24) #define S3C2410_DCON_CH3_SDI (1<<24) #define S3C2410_DCON_CH3_SPI (2<<24) #define S3C2410_DCON_CH3_TIMER (3<<24) #define S3C2410_DCON_CH3_USBEP4 (4<<24) +#define S3C2400_DCON_CH3_USBDEV (0<<24) +#define S3C2400_DCON_CH3_MMC (1<<24) +#define S3C2400_DCON_CH3_SPI (2<<24) +#define S3C2400_DCON_CH3_TIMER (3<<24) + #define S3C2410_DCON_SRCSHIFT (24) #define S3C2410_DCON_SRCMASK (7<<24)